This invention relates to high voltage semiconductor devices.
A significant problem inherent in semiconductor devices and circuits operating at high voltages (in excess of 30 volts) is the buildup of charge on the top surface of the outermost passivation layer. Among other adverse effects, such charge collection can cause a reduction in the breakdown voltage of the device due to inversion of the semiconductor surface.
In order to alleviate the problem, a field shield layer is typically employed. This layer is usually a semi-insulating layer which conducts enough current to neutralize the charge buildup without causing excessive leakage currents. Semi-insulating silicon nitride has been shown to be an excellent material for such purposes (see U.S. Patent Application of Knolle and Osenbach, Ser. No. 110,153 filed Oct. 19, 1987). Semi-insulating polycrystalline silicon has also been proposed (see, e.g., U.S. Pat. No. 4,009,483 issued to Clark).
Another problem has arisen, however, when such semi-insulating layers are employed. That is, conduction at the surface of the layer at sufficiently high voltages can cause arcing between electrodes through the air. This results in a considerable number of device failures during temperature-humidity-bias testing.
A further problem which often arises in high voltage applications is moisture-related corrosion failures. Such failures are apparently caused by water condensation in voids which exist in the semi-insulating or other layers. In the case of silicon nitride layers, the water etches the layer and also creates NH.sub.4.sup.+ ions. This reaction continues until it reaches the underlying metallization, and the water and ions then etch the metal causing a corrosion failure.
It is, therefore, an object of the invention to provide high voltage semiconductor devices with reduced failures due to arcing and corrosion.